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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Device Pin-to-Pin Input Parameter Guidelines
Table 46: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Speed Grade
Symbol
Description
Device
-3
-2/-2L
1.0V
-1
-1M
0.9V
-2L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15
Standard. (1)
Global Clock Input and IFF (2)
T PSFD /T PHFD
Full Delay (Legacy Delay or Default XC7K70T
Delay)
XC7K160T
2.83/–0.29 2.95/–0.29 3.15/–0.29
3.17/–0.35 3.29/–0.35 3.55/–0.35
N/A
N/A
4.96/–0.33
5.54/–0.49
ns
ns
without MMCM/PLL with
ZHOLD_DELAY on HR I/O Banks
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
2.83/–0.06 2.94/–0.06 3.15/–0.06
3.26/–0.32 3.41/–0.32 3.67/–0.32
3.43/–0.34 3.59/–0.34 3.88/–0.34
3.37/–0.27 3.48/–0.27 3.76/–0.27
3.37/–0.27 3.48/–0.27 3.76/–0.27
N/A
N/A
N/A
N/A
N/A
5.18/–0.14
5.84/–0.49
6.21/–0.54
6.00/–0.52
6.00/–0.52
ns
ns
ns
ns
ns
XQ7K325T
XQ7K410T
N/A
N/A
2.94/–0.06 3.15/–0.06 3.15/–0.06 5.18/–0.14
3.59/–0.34 3.88/–0.34 3.88/–0.34 6.21/–0.54
ns
ns
Notes:
1.
2.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch.
Table 47: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
-3
-2/-2L
1.0V
-1
-1M
0.9V
-2L
Units
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15
Standard. (1)
T PSMMCMCC / No Delay clock-capable clock input XC7K70T
T PHMMCMCC and IFF (2) with MMCM
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
2.39/–0.22 2.65/–0.22 2.94/–0.22
2.49/–0.20 2.77/–0.20 3.07/–0.20
2.55/–0.16 2.85/–0.16 3.14/–0.16
2.43/–0.16 2.73/–0.16 3.00/–0.16
2.55/–0.16 2.84/–0.16 3.14/–0.16
2.47/–0.09 2.73/–0.09 3.02/–0.09
2.47/–0.09 2.73/–0.09 3.02/–0.09
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2.21/–0.44
2.38/–0.47
2.60/–0.47
2.47/–0.43
2.58/–0.47
2.40/–0.41
2.40/–0.41
ns
ns
ns
ns
ns
ns
ns
XQ7K325T
XQ7K410T
N/A
N/A
2.85/–0.16 3.14/–0.16 3.14/–0.16 2.60/–0.47
2.84/–0.16 3.14/–0.16 3.14/–0.16 2.58/–0.47
ns
ns
Notes:
1.
2.
3.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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